Conventional practices for the manufacture of semiconductor devices comprise the formation of an element isolation region by a technique commonly known as Local Oxidation of Silicon (LOCOS). A conventional method of manufacturing a semiconductor device employing a LOCOS technique is disclosed in Japanese Patent Preliminary Publication No. Hei 5-182956. The initial step comprises the deposition of a first film, typically a silicon oxide film 2 on a silicon substrate 1, as shown in FIG. 8A. A first oxidation resistant film 3, typically a silicon nitride film, is deposited on the silicon oxide film 2. A resist film is then applied and patterned by conventional photolithographic and etching techniques. The patterned resist film 4 is employed as a mask for etching first silicon nitride film 3 and first silicon oxide film 2 to form an opening therethrough exposing the upper surface of silicon substrate 1 forming opening 5, as shown in FIG. 8B. Silicon substrate 1 is then etched to a predetermined depth to form groove 6 therein.
As shown in FIG. 8C, the resist film 4 is removed and the upper surface of silicon substrate 1 is thermally oxidized to form a second silicon oxide film 7 in the groove. As shown in FIG. 8D, a polycrystalline silicon film 8 is then deposited on silicon substrate 1. Polysilicon film 8 is then etched, typically by anisotropical etching, to expose the second silicon oxide film 7 at the bottom of groove 6, leaving a polysilicon sidewall 8a on the opening 5 and groove 6, as shown in FIG. 8E.
As shown in FIG. 9A, a second silicon nitride film 9 is deposited on silicon substrate 1. The second silicon nitride film 9 is etched, typically by anisotropic etching, to expose the silicon substrate at the bottom of groove 6 leaving a second silicon nitride sidewall 9a as a in opening 5 and groove 6 on polysilicon sidewall 8a, as shown in FIG. 9B. Silicon substrate 1 is then oxidized, as by thermal oxidation, using the first and second silicon nitride films 3 and 9a, respectively, as a mask, to form element isolation region 10, as shown in FIG. 9C.
During thermal oxidation in a conventional LOCOS process, second silicon nitride film 9a retards oxidation in a transverse direction; whereas, polysilicon film 8a relieves stress acting on silicon substrate 1 by second silicon nitride film 9a. Polysilicon film 8a oxidizes more readily than silicon substrate 1. Accordingly, oxidation of polysilicon sidewall 8a occurs more rapidly than that of silicon substrate 1, thereby promoting the oxidation of the silicon substrate in a transverse direction.
Subsequent to formation of the element isolation region, the first and second silicon nitride films 3 and 9a, respectively, are removed, as with hot phosphate. The first silicon oxide film 2 is then removed as by using hydrofluoric acid to complete element isolation region 10a shown in FIG. 9D.
There are several problems attendant upon conventional methods for manufacturing a semiconductor device employing a LOCOS technique, such as the conventional process described in FIGS. 8A through 9D. For example, during anisotropic etching in which the second silicon nitride sidewall 9a is formed, silicon substrate 1 is exposed at the bottom portion of the groove. Therefore, during anisotropic etching, ions are introduced into the silicon substrate 1 causing damage. Moreover, during thermal oxidation of silicon substrate 1, the second silicon nitride film 9a causes stress to silicon substrate 1 at the portion where there is no separating polysilicon film 8a. Portions of the silicon substrate damaged or stressed exhibit a higher oxidation rate than unstressed and undamaged portions. Moreover, the etching rate, particularly in hydrofluoric acid, is greater for oxidized portions which were not stressed or damaged than portions which have been stressed or damaged. As a result, it is difficult to obtain an element isolation region 10 with a relatively flat upper surface. An element isolation region having a relatively flat upper surface is desirable, because it is difficult to pattern a gate electrode and wirings after forming an element isolation region having a relatively non-uniform upper surface.
In addition to the foregoing, serious problems are generated in regions which have undergone stress from second silicon nitride film 9a. The increased stress from second silicon nitride film 9a generates a crystal lattice in silicon substrate 1, thereby increasing junction leakage current, deteriorating the refresh characteristics of a resulting DRAM and increasing the stand-by of the current device, thereby reducing the yield rate of products and impairing device characteristics.
Furthermore, in forming second silicon nitride sidewall 9a by removing second silicon nitride film 9 from the bottom of groove 6, silicon nitride film 9 is overetched by about 20 to about 30%. Consequently, the ratio of the thickness of the first silicon oxide film and first silicon nitride film is increased, thereby increasing the length of the bird's beak which is dependent upon the ratio of the thickness of the first silicon oxide film to the thickness of the first silicon nitride film.
Accordingly, there exists a need in the semiconductor industry for a LOCOS technique which overcomes the previously discussed problems attendant upon conventional practices to form an element isolation region using LOCOS.